The continuous growth of the semiconductor industry is due in no small part to the constant improvements in the integration density of electronic components (i.e., transistors, diodes, resistors, capacitors, etc.) by reducing their physical sizes to allow for a greater number of components to be placed in a given chip area. Some improvements are two-dimensional (2D) in nature in that the devices are fabricated on the surface of a semiconductor wafer. And even though advancements in lithography have enabled each new technology generation to feature smaller sizes than the previous one, there is an eventual physical limitation to the minimum size needed to make these components function properly. Additionally, when more devices are placed in one chip, the design complexity also increases.
One solution to solving the problems discussed above is to stack dies on top of one another and interconnect or route them through connections such as through-silicon vias (TSVs). Such a configuration is named a three-dimensional integrated circuit (3DIC). Some of the benefits of 3DIC, for example, include exhibiting a smaller footprint, reducing power consumption by reducing the lengths of signal interconnects, and improving yield and fabrication cost if individual dies are tested separately prior to assembly.
A typical problem with three-dimensional integrated circuit is heat dissipation during operation. Currently, most heat dissipation is performed by front side cooling with natural convection or by attaching a heat sink to the top of a package. In a 3DIC, for example, when a top die is stacked to a bottom die, a heat sink may be mounted on the top die. As a result, the top die may experience good heat-dissipating condition through natural convection with ambient air flow or with forced convection by utilizing a fan. However, the heat generated in the bottom die must travel through the potentially high thermal resistance of the top die in order to reach the heat sink. Hence, the bottom die may suffer from a heat-dissipation problem as the junction temperature will rise very quickly and exceed specifications. A prolonged exposure of a die by operating at excessive temperatures may decrease the reliability and operating lifetime of the die. This problem may become severe if the bottom die is a computing die such as a central processing unit (CPU), which generates a lot of heat.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale. Furthermore, dashed outlines depict regions where a layer or a component of the package is beneath or behind another layer or component.